AnalogAI Developed Sub-One-Watt Edge AI Processors

The new architecture enables on-device model training and adaptation by keeping computation local to stored data.

Updated on Sept. 23, 2026 in Semiconductors

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AnalogAI has introduced a new edge AI processor architecture that uses compute-in-memory technology to enable on-device model training under a one-watt power limit. AI Illustration. Upload story photo >

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AnalogAI has introduced edge AI processors utilizing Silicon Storage Technology's memBrain SAGE IP to operate under a one-watt power envelope. This technology allows for on-device model adaptation, avoiding the latency and power requirements of cloud-based retraining.

Why it matters

By enabling local model training within strict power constraints, this architecture addresses the efficiency bottlenecks currently limiting AI deployment at the network edge. It moves intelligence closer to data sources, reducing the reliance on high-latency cloud backhauls.

The memBrain architecture uses the Tensor In-Memory Logic Element (TILE), featuring an ESF3-based bitcell that stores up to 8 bits per cell. The platform is currently designed for 40nm and 28nm processes, with a 22nm roadmap in development.

The players

AnalogAI

A designer of edge AI processors focused on compute-in-memory architectures.

Silicon Storage Technology

A provider of embedded non-volatile memory technology including the SuperFlash memory system.

The details

The architecture performs computation directly where AI model data is stored, which minimizes energy-intensive data movement between memory and the processor. These chips combine analog compute-in-memory—a technique where mathematical operations occur within the memory array itself—with hardware-aware algorithms to facilitate on-device learning. By using SuperFlash non-volatile memory—a type of flash memory that retains data without power—the processors achieve high density and efficiency at the edge.

Timeline

  1. 2026-09-23

    The development was detailed in a report.

The Tech Race

This development follows a pattern set by industry efforts to move AI processing from the cloud to power-constrained edge hardware. The integration of 8-bit storage into a compute-in-memory architecture represents a specific competitive move to lower power consumption compared to traditional digital logic.

These processors enable real-time local model adaptation, meaning devices like IoT sensors or industrial equipment will soon gain the ability to learn from their environment without a cloud connection. Users will eventually see these benefits as device manufacturers incorporate the 40nm or 28nm chips into their hardware cycles.

The takeaway

The move toward sub-one-watt training signals a shift away from heavy reliance on massive data centers for machine learning updates. Watch for the 22nm roadmap deployment to determine how these efficiencies scale in mobile and battery-powered applications.

Further reading

For more on the latest developments in chip architecture and AI hardware, see Semiconductors.

Source note: This article includes information reported by Electronics For You - Official Site ElectronicsForU.com.

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