aiMotive and Cadence Demonstrated Multi-Engine AI Workloads
The joint simulation enables architects to distribute neural network layers across disparate processing units.
Updated on Sept. 28, 2026 in Artificial Intelligence
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aiMotive and Cadence have demonstrated a technique for splitting neural network workloads between aiWare5 and Tensilica NeuroEdge 130 AI processors. This pre-silicon simulation shows how distinct model layers can be assigned to different engines.
Why it matters
The development provides SoC architects with increased flexibility to balance AI tasks across heterogeneous compute engines. This approach allows designers to optimize hardware usage by matching specific network layers to the capabilities of different NPU architectures.
The simulation utilized the aiWare5 automotive NPU IP, which carries ISO 26262 ASIL B certification, alongside the Cadence Tensilica NeuroEdge 130 AI Co-Processor. The system successfully managed model execution without custom scheduling hardware.
The players
aiMotive
A developer of modular automated driving software and hardware IP, currently focused on NPU scaling and ISO 26262 compliant silicon architectures.
Cadence
A provider of computational software and design IP, known for the Tensilica processor line and comprehensive electronic design automation tools.
The details
Engineers achieved this distribution by manually annotating individual layers of the ResNet50 and DETR neural networks for specific engine execution. By mapping layers across toolchain boundaries, the simulation environment enables data processing to flow between the specialized aiWare5 architecture and the NeuroEdge co-processor. This cross-engine approach effectively decouples the neural network structure from the constraints of a single processing unit.
Timeline
September 28, 2026: aiMotive announced the joint technology demonstration.
The Tech Race
The collaboration marks a shift toward heterogeneous compute in automotive SoCs, moving away from reliance on singular, monolithic AI accelerators. This effort follows established trends in managing safety-certified ASIL B components within complex neural processing pipelines.
This development currently exists only within a pre-silicon simulation environment and does not yet impact production hardware. Future SoC designers will likely use these methods to optimize the power and latency profiles of automated driving systems.
The takeaway
The simulation proves that heterogeneous engine orchestration is technically feasible for standard network models like ResNet50. Observers should track upcoming silicon-level benchmarks to see if this design flexibility maintains performance targets in real-world automotive workflows.
Further reading
For more on evolving compute architectures, visit our coverage of Artificial Intelligence.
Source note: This article includes information reported by Design-reuse.
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