T2M Expanded RISC-V CPU IP Core Portfolio
The new 32-bit and 64-bit cores target scalable edge workloads with integrated vector and matrix processing.
Updated on Sept. 28, 2026 in Semiconductors
T2M has announced an expansion of its RISC-V CPU intellectual property portfolio, introducing new designs that span 32-bit and 64-bit architectures. These core designs are now available to chip developers looking to balance power and performance in system-on-chip designs.
Why it matters
As designers seek to optimize system-on-chip performance for edge computing, standardized instruction set architectures like RISC-V allow for greater flexibility in compute scaling. This expansion provides modular options for specific workload demands, such as vector-heavy AI tasks.
The TAE520 core utilizes a 6-stage superscalar in-order architecture to achieve 5.81 CoreMark/MHz. Meanwhile, the TDS550 combines 64-bit architecture with support for the RVV 1.0 vector processing standard and attached matrix extensions.
The players
T2M
A global provider of intellectual property for system-on-chip designs, specializing in ready-to-use processor cores and interface IP.
The details
The portfolio utilizes scalable single and multi-core architectures to handle varied computational loads. The TDS550 integrates CPU, vector (specialized math instructions for large data sets), and matrix (optimized math units for parallel processing) compute, allowing it to handle intensive edge workloads. Developers gain access to a software stack including GCC and LLVM—open-source compiler infrastructures—alongside GDB for debugging and QEMU for emulation of processor hardware.
Timeline
September 28, 2026: T2M announced the expansion of its RISC-V CPU IP core portfolio.
The Tech Race
This release positions T2M within the increasingly competitive ecosystem of modular RISC-V designs, where vendors race to provide standardized, highly efficient IP. The portfolio aims to keep pace with established proprietary alternatives by offering deeper integration of vector and matrix math units.
These core designs are intended for silicon engineers, enabling faster integration of custom compute blocks into new chips. End-product performance improvements will depend on how quickly manufacturers adopt these designs and ship devices utilizing the new vector processing capabilities.
The takeaway
T2M is signaling that specialized matrix extensions are now standard requirements for edge-computing processor IP. Watch for future benchmarks demonstrating how these new cores perform in real-world silicon implementations compared to incumbent Arm-based designs.
Further reading
For more on the evolving processor landscape, visit Semiconductors.
Source note: This article includes information reported by Design-reuse.
