TeraSignal Launched Analog Wave Processor Architecture
The new architecture enables signal processing in the analog domain to improve 200G/lane high-speed interconnects.
Updated on Sept. 29, 2026 in Semiconductors
TeraSignal has released its new Analog Wave Processor architecture, which performs mathematical operations directly on broadband electrical waveforms. This architecture is now integrated into the company's Lotus 200G/lane product family.
Why it matters
As high-speed interconnects push toward 200G per lane, managing channel impairments has become a critical engineering challenge. This architecture aims to address those distortions by processing signals in the analog domain before they reach digital conversion.
The processor manages weighting, delay, and accumulation in the analog domain to support 200G per lane operations. It is integrated into the TS5802 copper redriver, TS8802 linear MZM driver, and TS9802 linear TIA.
The players
TeraSignal
A developer of high-speed interconnect silicon and signal-processing architectures for data center infrastructure.
The details
The architecture operates by performing wave-domain feed-forward equalization, a technique used to compensate for signal distortion, specifically correcting for precursor and postcursor intersymbol interference (ISI) — the overlap of signal pulses that causes data errors. By executing these mathematical operations directly on the broadband electrical waveform, the system handles channel impairments without needing to convert the signal to digital form first. This design supports multiple deployment configurations, including ACC (Active Copper Cable), LPO (Linear Pluggable Optics), NPO (Near-Packaged Optics), and CPO (Co-Packaged Optics).
Timeline
September 29, 2026: TeraSignal announced the Analog Wave Processor architecture.
The Tech Race
This architecture aims to solve signal integrity issues in the 200G-per-lane race, positioning itself against traditional digital-heavy equalization methods. It specifically targets the performance limitations of current copper and optical interconnects to enable future speeds beyond 200G.
This technology is integrated into the Lotus 200G/lane product family, which serves data center engineers and high-performance computing architects. It requires no immediate user action, as the components are designed for future high-speed hardware infrastructure.
The takeaway
The move to analog domain processing represents a shift toward more efficient signal correction at multi-hundred gigabit speeds. Watch for performance data releases in upcoming test cycles as the Lotus product family moves into wider deployment in data center architectures.
Further reading
For more developments in high-speed hardware design, see our coverage of Semiconductors.
Source note: This article includes information reported by Embedded Computing Design.
