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MIPS Collaborated With Chinese Firms on RISC-V Standards

The U.S. chip IP provider aligned with local companies to expand adoption of the open-standard architecture.

Updated on Oct. 3, 2026 in Semiconductors

Bold flat-color editorial illustration of a silicon semiconductor wafer, representing the standardization of RISC-V chip architecture.
MIPS has collaborated with Chinese firms to standardize RISC-V platforms, supporting national goals to reduce reliance on proprietary chip architectures. AI Illustration. Upload story photo >

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In September 2026, U.S.-based chip IP provider MIPS engaged with Chinese firms to standardize RISC-V platforms, a move central to China's 15th five-year plan. The collaboration supports a growing ecosystem designed to reduce dependence on proprietary architectures like x86 and Arm.

Why it matters

RISC-V provides an open, customizable alternative to established proprietary stacks, making it a strategic priority for national electronics goals. This collaboration accelerates the adoption of these energy-efficient designs across high-performance AI and robotics applications.

MIPS employs 700 engineers to support RISC-V deployments. The architecture's appeal stems from its openness and energy efficiency compared to the traditional Intel x86 or Arm instruction sets.

The players

MIPS

A U.S.-based intellectual property provider owned by GlobalFoundries that supplies chip architecture platforms.

Eswin Computing Technology

A semiconductor company preparing for an initial public offering on the Hong Kong stock exchange.

RISC-V International

The global governing body that manages the open-standard instruction set architecture for chip design.

The details

RISC-V is an open-standard instruction set architecture — the fundamental set of commands a processor uses to execute software — that allows designers to create custom central processing units. MIPS provides the platform layers for these designs, which are now being adapted beyond original data center use cases to power humanoid robotics via repurposed Advanced Driver Assistance Systems, or systems that use sensors and AI to automate vehicular safety features.

Timeline

  1. July 2026: Qi Xiaoning spoke at the SCMP China Conference.

  2. September 2026: Yankin Tanurhan held a media briefing in Shanghai.

  3. September 2026: Liu Shuai spoke at an industry event.

  4. September 2026: China released its 15th five-year plan policy document.

  5. October 9, 2026: Eswin Computing Technology IPO scheduled.

The Tech Race

This collaboration marks a significant step in the global race to establish RISC-V as a viable alternative to entrenched proprietary architectures. It follows the integration of these open standards into the core of China's 15th five-year plan for electronics.

This development impacts the hardware supply chain rather than immediate end-user products. Future devices, particularly in robotics and high-performance computing, will increasingly rely on these standardized RISC-V blocks for energy-efficient processing.

The takeaway

The move signals a hardening of RISC-V as a global architectural standard with institutional backing from major economies. Watch for the Eswin Computing Technology IPO on October 9, 2026, as a barometer for investor sentiment toward firms centered on this open-standard roadmap.

Further reading

For more on the industry shift toward open architectures, visit Semiconductors.

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Should companies in rival nations collaborate on developing shared technology standards like open-source chips?