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Cadence Launched RTL Agent for Automated Chip Design

The new tool automates front-end chip design and verification, offering performance gains over standard AI models.

Updated on Sept. 29, 2026 in Semiconductors

Isometric editorial illustration of a silicon wafer with complex circuit patterns, representing semiconductor design technology.
Cadence Design Systems announced its new RTL Generation Agent, a tool designed to automate digital circuit design and verification through natural language specifications. AI Illustration. Upload story photo >

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Cadence has announced the launch of its RTL Generation Agent, a tool designed to automate front-end digital design and verification. The agent, which converts natural language prompts into register-transfer level (RTL) code, is currently an announced product.

Why it matters

By automating the creation and refinement of RTL, the agent seeks to accelerate design productivity from initial specification to functional code. This capability supports the adaptation of legacy code to new requirements in semiconductor development.

The RTL Generation Agent demonstrated a 24% area reduction and an 18% power reduction compared to pure foundation model code generation, while maintaining 100% functional accuracy. The system leverages task-specific agents that integrate directly with existing electronic design automation software.

The players

Cadence

A developer of electronic design automation software and hardware used for integrated circuit design.

Honda

An automotive manufacturer currently evaluating the RTL Generation Agent for system-on-chip development.

The details

The agent operates by converting natural language specifications into RTL, the digital design language used to model electronic circuits. It utilizes task-specific agents that interface with electronic design automation (EDA) software—tools used to design and verify complex integrated circuits—to perform design analysis and code refinement. This process allows engineers to generate new designs or modify legacy RTL to meet modern requirements.

Timeline

  1. February 2026: Cadence announced its first agentic workflow for front-end design.

  2. June 2026: The company announced an autonomous virtual engineer for chip design.

  3. September 29, 2026: Cadence launched the RTL Generation Agent.

  4. Q4 2026: Expanded capabilities become available to early-access customers.

The Tech Race

This development follows the trajectory set by the ChipStack and InnoStack AI Super Agent initiative to move beyond general-purpose LLMs in chip design. It represents an industry push to transition from general code generation to domain-specific, PPA-driven automated workflows.

Engineers and chip architects should watch for the Q4 2026 early-access window to begin testing the agent in their existing design workflows. The tool is specifically intended for professionals managing front-end digital design and those seeking to modernize legacy RTL codebases.

The takeaway

The RTL Generation Agent signals a shift toward specialized AI agents that prioritize functional accuracy and power efficiency over generic code generation. Industry practitioners should monitor the Q4 2026 early-access deployment for performance metrics in real-world automotive SoC projects.

What happens next

Select early-access customers will gain access to the expanded ChipStack and InnoStack AI Super Agent capabilities in Q4 2026.

Further reading

For more on how automated design is evolving, visit our Semiconductors section.

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