AMD Engineering Sample Ryzen 9 5900X3D Surfaced

A leaked engineering sample reveals a single-chiplet 12-core configuration that AMD previously cancelled.

Updated on Oct. 2, 2026 in Semiconductors

Isometric editorial illustration of a silicon processor die with a vertically stacked cache layer, representing advanced computer hardware architecture. — Leaked images of an AMD Ryzen 9 5900X3D engineering sample reveal a cancelled 12-core processor configuration that utilized 3D V-Cache technology. AI Illustration. Upload story photo >

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Images from the Chiphell forums display an unreleased AMD Ryzen 9 5900X3D engineering sample. This processor features a 12-core, 24-thread configuration and 128 MB of L3 cache.

Why it matters

The appearance of this sample provides a rare look at a processor variant that was officially cancelled by AMD after prior demonstrations. It highlights the design trade-offs between cache density and clock speed in high-performance computing.

The sample utilizes a 128 MB L3 cache, derived from a 32 MB base with a 96 MB 3D V-Cache chiplet stacked on a single CCD. Diagnostic tools reported boost clocks of 4.65 GHz and 4.73 GHz, exceeding the 4.4 GHz limit seen in dual-CCD variants.

The players

AMD

A designer of CPUs, GPUs, and adaptive SoCs that competes directly with Intel and NVIDIA in both the consumer and data center markets.

Chiphell

A prominent hardware-focused forum often serving as the primary source for early component leaks and engineering sample documentation.

The details

The design utilizes 3D V-Cache, a technology where a cache memory die is stacked vertically on top of the processor core die to increase memory capacity. By using a single-chiplet design rather than the dual-CCD configuration, the sample achieves higher frequency ceilings compared to previous versions. CPU-Z and secondary monitoring tools confirmed the processor operates as a 12-core, 24-thread unit.

Gamers Nexus visited the AMD campus to view unreleased processors in 2023.
A report regarding the spotted engineering sample was published on October 2, 2026.

The Tech Race

The emergence of this sample marks a departure from the dual-CCD implementation of AMD's 3D V-Cache architecture. It highlights the internal hardware competition to balance massive cache integration against core heat constraints.

This engineering sample is not a commercial product and will not be available for retail purchase. Enthusiasts and developers can observe how these specific cache configurations influence future retail chip performance benchmarks.

The takeaway

This discovery serves as a reminder of the complex design iterations that occur behind the scenes at semiconductor firms before a product reaches the market. Watch for official AMD performance documentation or future roadmap updates that might clarify why single-CCD V-Cache configurations were ultimately deprioritized.