Cerebras Secured $25.4 Billion Sales Backlog

The company leverages 5nm wafer-scale chips to bypass industry-wide bottlenecks in high-bandwidth memory supply.

Updated on Oct. 4, 2026 in Semiconductors

Isometric editorial illustration of a circular silicon wafer featuring a dense, integrated circuit pattern, representing semiconductor manufacturing technology. — Cerebras Systems reported a $25.4 billion sales backlog as the company scales its wafer-scale architecture to circumvent traditional semiconductor supply constraints. AI Illustration. Upload story photo >

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Cerebras Systems has reported a $25.4 billion sales backlog as it expands its AI-focused semiconductor operations. The company is scaling its infrastructure to meet demand for its wafer-scale architecture, which uses on-chip memory to avoid common supply chain constraints.

Why it matters

By integrating all memory directly onto the chip, Cerebras circumvents industry chokepoints like HBM and CoWoS packaging. This design allows the firm to maintain production velocity while competitors contend with limited advanced manufacturing capacity.

The WSE-3 chip utilizes TSMC's 5nm process node to pack 4 trillion transistors and 900,000 AI cores across a 46,225 mm² surface area. The architecture provides 44 GB of on-chip SRAM, eliminating the need for separate HBM (high-bandwidth memory) stacks.

The players

Cerebras Systems

A semiconductor company focused on wafer-scale AI processors that integrate compute and memory on a single die.

OpenAI

An AI research and development firm that accounts for over $20 billion of the reported sales backlog.

Gimlet Labs

A research entity that has committed to a 100 MW capacity supply agreement with Cerebras.

Andrew Feldman

The CEO of Cerebras Systems who leads the strategic direction and market positioning of the company's wafer-scale tech.

The details

The WSE-3 operates by centralizing processing and memory on a single wafer-scale die. By using on-chip SRAM (static random-access memory — a type of fast memory that holds data without needing constant refreshing) instead of HBM (specialized memory chips stacked to increase bandwidth), the system avoids the need for CoWoS (chip-on-wafer-on-substrate) packaging, which is currently a primary constraint for many AI chip manufacturers. This integration allows Cerebras to sidestep competition for 3nm manufacturing capacity while relying on established 5nm nodes.

March 2024: Cerebras announced the WSE-3 chip.
May 2026: Cerebras completed a Nasdaq IPO.
June 2026: CEO Andrew Feldman discussed inference performance.
September 2026: Cerebras agreed to supply Gimlet Labs.
Q1 2027: Planned deployment for the General Compute agreement.

The Tech Race

The Cerebras design marks a departure from the industry-standard HBM and CoWoS-based AI accelerator packaging by favoring monolithic wafer-scale SRAM integration. This architecture prioritizes throughput by ignoring the current race to 3nm processes that drive competitor roadmaps.

The firm’s backlog primarily impacts large-scale enterprise data centers and research labs that require high-compute density. Individual developers and small firms will not see direct hardware availability until the company expands its manufacturing partnerships and increases total operational capacity.

The takeaway

Cerebras has built a massive backlog by effectively opting out of the constrained supply chains currently plaguing the wider AI industry. Watch for future quarterly reports to confirm if the firm can scale its manufacturing to meet the 100 MW target for the Q1 2027 deployment window.