Applied Materials and Intel Formed Semiconductor Partnership

The companies aim to accelerate the development of next-generation transistor and advanced packaging architectures.

Updated on Oct. 6, 2026 in Semiconductors

Bold flat-color editorial illustration of a stacked silicon wafer architecture, representing technical semiconductor collaboration. — Applied Materials and Intel have entered a strategic partnership to co-develop advanced 3D packaging and transistor architectures for next-generation AI computing. AI Illustration. Upload story photo >

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Applied Materials and Intel have announced a collaboration to develop advanced transistors, interconnects, and Foveros-based 3D stacking technologies. The joint research efforts are intended to address the growing performance and power efficiency demands of AI computing workloads.

Why it matters

This partnership seeks to shorten development cycles and time-to-market for future semiconductor nodes by integrating material engineering with device architecture. It reflects an industry-wide push to optimize silicon for the specific compute requirements of large-scale AI.

The collaboration leverages the EPIC Center in Silicon Valley alongside Intel's R&D campus in Hillsboro, Oregon. It focuses on Foveros 3D stacking—a method of integrating multiple logic or memory chips vertically to increase density and performance.

The players

Applied Materials

A leader in materials engineering solutions, specializing in equipment and software for manufacturing semiconductor chips.

Intel

A primary designer and manufacturer of microprocessors, focused on advancing x86 architecture and 3D chip packaging technologies.

The details

Engineers from both firms are integrating material engineering with process technologies to refine how signals travel between transistors. The work focuses on improving interconnects, the conductive pathways connecting individual components on a chip, to minimize energy loss. By co-developing these at the architecture level, the teams aim to optimize how Foveros-based 3D chips manage thermal output and data density.

October 6, 2026: Applied Materials and Intel announced their collaboration.
2026: The EPIC Center is scheduled to be operational.

The Tech Race

This effort builds upon the shift toward heterogeneous integration, where companies rely on sophisticated 3D stacking to bypass physical limitations of traditional 2D scaling. It mirrors competitive industry trends to secure internal R&D pipelines for custom AI-optimized silicon.

While this collaboration targets long-term R&D, it aims to speed up the availability of more efficient chips for future AI platforms. Users should expect these design improvements to influence future hardware performance once the EPIC Center reaches full operation in 2026.

The takeaway

This partnership marks a strategic alignment intended to solve material limitations in 3D-stacked AI chips. Watch for future benchmarks or white papers released from the EPIC Center once it becomes operational in 2026.