IBM Releases 0.7-Nanometer Manufacturing Kits

The new design tools help engineers implement vertical transistor stacking to improve memory scaling by 40%.

Updated on Oct. 16, 2026 in Semiconductors

Isometric editorial illustration showing a complex silicon wafer structure with dense vertical transistor layers in teal, mustard, and slate blue. — IBM launched process development kits for its 0.7-nanometer Nanostack chip manufacturing technology, enabling designers to evaluate vertical transistor stacking architectures. AI Illustration. Upload story photo >

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IBM has released process development kits for its 0.7-nanometer Nanostack chip manufacturing technology, a design platform introduced in June 2026. These kits provide the necessary tools for chip designers to begin evaluating the architecture, with full availability scheduled for the first quarter of 2027.

Why it matters

As transistor gate lengths fall below 3 nanometers, traditional scaling faces critical hurdles with current leakage and signal propagation. This architecture aims to mitigate these physical constraints by optimizing transistor density and power consumption, particularly for SRAM-heavy hardware.

The 0.7-nanometer (seven angstrom) technology utilizes a vertical stacking and staggering method for n-type and p-type transistors. This approach targets SRAM, which currently occupies up to 15% of the total die area for chips like the NVIDIA Hopper H100, including L1 cache.

The players

IBM

A legacy technology company focused on enterprise computing, semiconductor R&D, and hybrid cloud infrastructure.

NVIDIA

A designer of graphics processing units and data center accelerators that currently utilizes large SRAM caches in its Hopper H100 chip architecture.

The details

Nanostack technology employs a 3D-integration method that vertically stacks and staggers transistors to manage the layout. The process development kits include design rule manuals, design rule checking, and electronic design automation (EDA) layout scripts. These tools allow engineers to simulate how the vertical arrangement interacts with signal propagation at the sub-nanometer level, effectively addressing the leakage issues common in extremely short gate lengths.

June 2026: IBM officially launched the 0.7-nanometer Nanostack chip manufacturing technology.
First quarter 2027: IBM expects to release process development kits to external chip designers.

The Tech Race

This development moves beyond current sub-3-nanometer efforts by introducing 3D transistor staggering to overcome standard planar limitations. It positions IBM's process design tools against the existing scaling trajectory of established high-performance data center architectures.

Chip designers will gain access to the evaluation kits in early 2027 to begin integrating the Nanostack architecture into future silicon roadmaps. The primary beneficiaries will be developers of high-density AI and data center processors seeking to reduce SRAM footprint and improve power efficiency.

The takeaway

Designers should monitor the Q1 2027 rollout of these development kits to assess if the 40% SRAM scaling projection holds in EDA layout simulations. Future benchmark releases from IBM will indicate if this 0.7-nanometer process can successfully maintain performance while suppressing current leakage.