Orthogone Released Ultra-Low-Latency FPGA IP Portfolio
The new suite enables sub-microsecond packet processing on AMD adaptive platforms for high-performance computing.
Updated on Oct. 7, 2026 in Semiconductors
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Orthogone has released a production-ready portfolio of FPGA IP cores designed to accelerate networking and data movement on AMD UltraScale+ and Versal adaptive platforms. The suite performs packet processing tasks within sub-microsecond latency thresholds.
Why it matters
By offloading network operations from host CPUs to FPGA logic, this portfolio provides the determinism and low jitter required for compute-intensive sectors like aerospace, defense, and quantum research.
The portfolio supports Ethernet line rates at 1G, 10G, 25G, 40G, and 100G, incorporating an optional Reed-Solomon forward error correction (FEC) layer. It also features a PCIe circular-buffer direct memory access (DMA) controller supporting Gen3 and Gen4 interfaces.
The players
Orthogone
An engineering firm providing high-performance FPGA and networking IP cores for specialized hardware ecosystems.
AMD
A semiconductor developer providing adaptive computing platforms including the UltraScale+ and Versal architectures.
The details
The IP cores function by offloading network processing from the host CPU to specialized FPGA logic, which allows for faster data handling. A DMA controller — a hardware module that moves data between main memory and peripheral devices without CPU intervention — facilitates bidirectional traffic between the host and the FPGA over PCIe. The inclusion of TCP/IP and UDP/IP offload engines allows for efficient packet management at wire speed.
Timeline
October 7, 2026: Orthogone announced the portfolio availability.
The Tech Race
This release follows the trend of moving networking stacks into hardware to minimize processing bottlenecks in time-sensitive fields. It positions the portfolio as a direct rival to existing proprietary networking solutions for AMD's high-end adaptive computing ecosystem.
Engineers building aerospace or quantum systems can now integrate these cores directly into their AMD-based development workflows. Hardware availability is immediate for those utilizing standard UltraScale+ and Versal development environments.
The takeaway
This portfolio demonstrates the industry's continued shift toward hardware-level network offloading to meet stringent latency requirements. Watch for future benchmarks regarding jitter performance when operating at the maximum 100G line rate.
Further reading
For broader trends in hardware acceleration, see our coverage in Semiconductors.
Source note: This article includes information reported by EDN.
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