Siemens Releases Tessent Software for Chip Test Execution
The software integrates into automated testing hardware to support high-speed PCIe Gen 6 chip designs.
Updated on Oct. 21, 2026 in Semiconductors
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Siemens has released the Tessent Silicon Executable software, which is designed to integrate chip test creation directly into automated test equipment (ATE). This software enables testing across high-speed interfaces like PCIe Gen 6 by bridging the gap between test pattern generation and execution.
Why it matters
As semiconductor designs reach higher complexity and operating frequencies, traditional testing methods have become increasingly time-consuming. This software aims to address these bottlenecks by streamlining the application of test patterns within existing industry-standard hardware.
The platform now supports testing over PCIe Gen 6 interfaces, an upgrade from prior generations. It achieves this by embedding directly into automated test environments to link test collateral to physical execution.
The players
Siemens
A multinational technology conglomerate that provides industrial software, including design-for-test tools for semiconductor development.
Advantest
A manufacturer of automated test equipment that has integrated the new software into its V93000 platform.
Teradyne
A developer of automated test equipment that has integrated the software into its UltraPort instrument for the UltraFLEXplus system.
The details
The software functions by consuming Tessent-generated collateral and applying test patterns directly through the target execution environment. This mechanism embeds into automated test equipment to create a tighter link between test design and application. The approach replaces traditional, disconnected workflows with a unified execution path designed to handle the increasing complexity of high-frequency semiconductor architectures.
Timeline
October 20, 2026: Siemens announced the Tessent Silicon Executable software.
The Tech Race
This release aligns with the industry movement toward standardized support for PCIe Gen 6 architectures in test equipment. It directly positions the Siemens software against traditional test methods by integrating with major ATE platforms to keep pace with rapid advancements in chip speed.
Semiconductor manufacturers and hardware engineers can now use this software to test high-speed PCIe Gen 6 interfaces on existing Advantest V93000 and Teradyne UltraFLEXplus platforms. Availability is immediate, with the tool acting as an integration layer for current automated test workflows.
The takeaway
The industry is shifting toward more integrated test environments to manage the throughput demands of next-generation high-speed interfaces. Watch for benchmark reports from early adopters to confirm if this software successfully reduces total test duration compared to legacy methods.
Further reading
For more on industry-wide developments in chip testing, explore our Semiconductors section.
Source note: This article includes information reported by DQ.
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