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Tenstorrent Releases Open Chiplet Design Framework

The beta framework provides management tools to streamline the integration of modular, multi-chiplet silicon designs.

Updated on Oct. 26, 2026 in Semiconductors

Isometric editorial illustration of modular silicon chiplet components arranged in a neat technical grid.
Tenstorrent released the beta version of its Open Chiplet Atlas framework, a new toolset intended to standardize chiplet-based processor design and interoperability. AI Illustration. Upload story photo >

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Tenstorrent has released the open-source beta of its Open Chiplet Atlas (OCA) Harness, a design framework aimed at simplifying multi-chiplet development. The beta release includes the complete register-transfer level (RTL) code, an integrated security processor, and a system management controller.

Why it matters

The framework is designed to lower non-recurring engineering costs and integration risks for teams building complex modular processors. By providing standardized communication and management interfaces, it aims to accelerate the adoption of chiplet-based architectures.

The beta provides three primary management subsystems—a security processor, system management controller, and debug ports—all integrated via an OCA System Management Unit. It supports AXI4 traffic over Universal Chiplet Interconnect Express (UCIe) links, utilizing an AXI over UCIe RTL implementation contributed by BOS Semiconductors.

The players

Tenstorrent

A compute company developing AI hardware, RISC-V processors, and open-source chiplet interconnect technologies.

BOS Semiconductors

A semiconductor design firm that contributed the AXI over UCIe RTL for this framework.

lowRISC

A non-profit organization focused on open-source silicon development that assisted in the project.

The details

The framework functions by providing a standardized architecture for chiplet interoperability, transforming high-level design specifications into reusable, deployable RTL—a high-level hardware description language used to model electronic circuits. It includes a C++/SystemC virtual platform, which acts as a software-based emulator, allowing developers to begin firmware testing before physical silicon is available. The system relies on the OCA AoU (Adapter over UCIe) to handle communication between separate chiplets, ensuring cross-chiplet access for testing and management.

Timeline

  1. October 26, 2026: Tenstorrent released the open-source beta.

  2. January 2027: The full release of the framework is currently targeted.

The Tech Race

This framework serves as a critical software layer for the growing ecosystem of UCIe-based chiplet designs. It addresses the lack of standardized management infrastructure, which currently remains one of the largest bottlenecks for teams attempting to mix-and-match chiplets from different vendors.

Engineers and chiplet developers can now access the virtual platform on GitHub to begin firmware development and simulation without waiting for physical prototypes. While the beta is available for testing, the production-grade full release remains scheduled for January 2027.

The takeaway

This release provides a standardized path for modular chip development that previously lacked an open management layer. Developers should track the project's progression toward the full release in January 2027 to see how the framework evolves for production use cases.

Further reading

For more on modular hardware standards, see our Semiconductors section.

More information

Access the technical documentation and source code at the OCA Harness GitHub repository.

Source note: This article includes information reported by Design-reuse.

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