IBM Unveils Vertical Transistor Design to Boost Efficiency
The new architecture aims to overcome Moore's Law limits by stacking transistors to cut energy waste by 85%.
Updated on Oct. 27, 2026 in Semiconductors
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IBM has unveiled a prototype chip featuring vertically stacked transistors developed at its Albany, New York, Nanotech Center. This design enables electrical current to flow perpendicular to the chip surface, marking a shift toward new architectures as Moore's Law constraints tighten.
Why it matters
By stacking transistors vertically, this architecture overcomes the physical space limitations of traditional two-dimensional chip layouts. The development aims to scale performance while significantly curbing energy waste in high-demand computing systems.
The vertical transistor design achieves an 85% reduction in energy usage compared to current standards by allowing for more efficient electrical current flow. This architecture represents a departure from traditional seven-nanometer chips, such as those currently used in Power 10 servers.
The players
IBM
A technology conglomerate focused on high-performance enterprise computing, mainframes, and advanced semiconductor research.
Samsung
A global semiconductor manufacturer that produces chips for external partners and maintains a large-scale foundry business.
The details
The technology implements transistors perpendicular to the chip surface, a technique known as Vertical Transport Field Effect Transistors (VTFET). Traditional chips arrange transistors flat across a surface; this vertical stacking allows engineers to increase the number of transistors on a single chip without expanding its physical footprint. By facilitating an up-and-down current flow, the design bypasses the spacing constraints that typically limit performance gains in silicon-based microprocessors.
Timeline
1965: Gordon Moore establishes the principle known as Moore's Law.
October 2026: IBM unveils the vertical chip design prototype.
2024: The company expects the new chips to become available.
The Tech Race
This development follows industry-wide efforts by competitors like Intel and TSMC to move beyond traditional planar transistor scaling. It positions IBM to address the physical limits of Moore's Law through architecture changes rather than just shrinkage.
The technology is slated for use in future Power series and Z series mainframes, with commercial availability expected in 2024. Future consumer applications could eventually include mobile devices with significantly extended battery life, though no specific consumer hardware releases have been announced.
The takeaway
IBM's move to vertical transistors signals that the industry is aggressively pivoting toward structural architecture changes to maintain performance growth. Watch for the 2024 commercial rollout to see how the energy efficiency claims translate into real-world mainframe data center metrics.
Further reading
For broader trends in chip architecture, see the latest updates on Semiconductors.
Source note: This article includes information reported by TechTarget.
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