TetraMem Tapes Out 12nm MLX300 In-Memory Computing Chip
The new 12nm system-on-chip is designed to support 64 million parameters and improve AI energy efficiency.
Updated on Oct. 27, 2026 in Semiconductors
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TetraMem has completed the tapeout of its MLX300 system-on-chip, an analog in-memory computing processor. The device is currently in the design stage following the tapeout milestone.
Why it matters
By integrating memory and compute processing, the MLX300 seeks to eliminate the data movement bottlenecks that limit energy efficiency in traditional AI architectures.
The MLX300 is built on a 12nm process node, a significant shrink from the 22nm MLX200. It targets a power efficiency range of 50-80 TOPS/W for on-chip inference.
The players
TetraMem
A San Jose-based startup developing analog in-memory computing chips for machine learning workloads.
Synopsys
A provider of electronic design automation software and cloud-based engineering environments.
The details
The MLX300 utilizes multi-level RRAM (Resistive Random Access Memory) to integrate processing logic directly within the memory array. This architecture allows the chip to store and process up to 64 million INT4 parameters locally, removing the need for external DRAM (Dynamic Random Access Memory) that typically causes energy-heavy data transfer bottlenecks. Design teams used Synopsys Cloud FlexEDA tools to accelerate RTL (Register Transfer Level) verification by 3x.
Timeline
2026: TetraMem completed two full-mask SoC tapeouts.
October 27, 2026: TetraMem announced the MLX300 tapeout.
The Tech Race
The MLX300 represents a direct generational advancement over the 22nm MLX200, shifting to a 12nm process to improve parameter capacity. The startup is moving to denser nodes to compete with conventional digital AI accelerators for edge-computing energy efficiency.
This chip remains in the design and pre-production phase following the recent tapeout. Once manufactured, the hardware aims to enable high-efficiency AI inference for edge devices that require local data processing.
The takeaway
TetraMem is signaling a move toward higher parameter density by shrinking its process node from 22nm to 12nm. Watch for the eventual release of physical silicon benchmarks, which will confirm whether the architecture hits its targeted 50-80 TOPS/W efficiency threshold.
Further reading
For more on the current state of specialized AI hardware, visit Semiconductors.
Source note: This article includes information reported by Financial Post.
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