Google Splits Its TPUs for Training and Inference

The claimed 80% performance-per-dollar gain over Ironwood is announced, with general availability expected later in 2026.

Updated on Nov. 9, 2026 in Semiconductors

Isometric editorial illustration of two matte rectangular processor modules side by side, one with fine grid lines and one with stacked memory layers, joined by a thin copper-toned bridge. — Google unveiled its eighth-generation TPUs on April 22, 2026, splitting the line into a training chip and an inference chip, with general availability expected later this year. AI Illustration. Upload story photo >

Google unveiled its eighth-generation Tensor Processing Units on April 22, 2026, at Cloud Next, split into two separate designs for the first time: the TPU 8t for large-scale pre-training and the TPU 8i for inference and high-concurrency reasoning. Both are announced rather than shipped, with general availability expected later in 2026.

Why it matters

Splitting a TPU generation into distinct training and inference designs reflects Google's framing of the agentic era, in which AI systems juggle many tasks at once. The move signals that the workloads now demand specialized silicon rather than one chip optimized for both.

The TPU 8t pairs 216 GB of High Bandwidth Memory with 128 MB of Static Random-Access Memory, while the TPU 8i carries 288 GB of High Bandwidth Memory and 384 MB of Static Random-Access Memory. Both chips are manufactured on TSMC's N3 process and integrate Google's Arm-based Axion CPUs, though the 80% performance-per-dollar advantage over Ironwood remains a vendor claim.

The players

Google

Alphabet's cloud and AI division, which designs its own TPU accelerators alongside Axion Arm-based CPUs and runs them in its AI Hypercomputer stack.

TSMC

Taiwan Semiconductor Manufacturing Company, the contract chipmaker that fabricates both TPU 8 designs on its N3 process.

The details

Both chips slot into Google's AI Hypercomputer architecture, the company's system for connecting many accelerators into a single large machine. The TPU 8t scales into superpods of up to 9,600 chips, while the TPU 8i adds a new Boardfly topology, a way of wiring chips together to cut communication delays, and a CAE engine. High Bandwidth Memory — fast memory stacked close to the processor — is the key resource for these workloads, and the split reflects different memory and compute balances for training versus serving.

April 22, 2026: Google unveiled the eighth-generation TPUs at Cloud Next.
August 2026: Hot Chips 2026 is slated to bring more technical detail.
Later in 2026: General availability of the new chips is expected.

The Tech Race

Google's split of the TPU line into training and inference chips follows its own Ironwood launch in 2025 and positions the company against accelerator roadmaps from other hyperscalers. The move suggests the contest is shifting toward specialized silicon for distinct AI workloads rather than general-purpose accelerators.

The chips are not yet available, with general availability expected later in 2026 through Google Cloud. Customers running large training jobs or high-volume inference are the likeliest first users, and the claimed performance-per-dollar gain would matter most to them once pricing is known.

The takeaway

The bigger signal is that Google now treats training and inference as workloads deserving different silicon. Watch Hot Chips 2026 in August for independent detail on the 80% performance-per-dollar claim against Ironwood.

What happens next

Google plans to share more technical details at Hot Chips 2026 in August, and general availability of the TPU 8t and TPU 8i is expected later in 2026.