Nagare Labs Secures Funding for Z2RAM Development
The startup plans to sample its new high-density memory architecture by 2030 to challenge current SRAM limitations.
Updated on Oct. 26, 2026 in Semiconductors
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Nagare Labs has secured $5 million in seed funding to advance its Z2RAM memory technology, which is currently at the lab-prototype stage. This research-stage memory uses oxide semiconductors to achieve higher bit density than traditional SRAM.
Why it matters
Nagare Labs is attempting to bridge the performance and density gap between current memory technologies by vertically stacking cells on compute logic. If successful, this could significantly increase on-chip memory capacity for high-performance computing tasks.
The Z2RAM architecture uses two transistors per cell, offering a 320 MB capacity per tile compared to 64 MB for equivalent SRAM. It aims to eventually scale memory capacity closer to the density levels required for modern AI accelerators.
The players
Nagare Labs
A research-oriented startup originating from Georgia Institute of Technology focused on developing Z2RAM memory.
Playground Global
A venture capital firm that invests in deep tech and hardware startups, recently adding Pat Gelsinger as a partner.
Sumem Datta
A founder of Nagare Labs who is leading the development of Z2RAM technology.
Shimeng Yu
A co-founder of Nagare Labs and researcher focused on semiconductor memory innovation.
Pat Gelsinger
A partner at Playground Global and current executive at Intel who influences early-stage hardware investment.
The details
Z2RAM functions by storing charge within the gate capacitance of a second transistor, a departure from traditional single-transistor DRAM designs. Nagare Labs plans to implement this via 3D hybrid bonding, a process that physically stacks memory cells directly atop compute logic layers. Researchers must overcome the tendency of the utilized oxide semiconductors to form atomic vacancies, which can degrade electrical reliability.
Timeline
2025: Pat Gelsinger joins Playground Global as a partner.
2030: Target date for sampling working Z2RAM memory tiles.
2036: Target year for initial production shipments.
The Tech Race
Nagare Labs is competing to solve the 'memory wall' that currently limits throughput in AI accelerators like those from Nvidia and AMD. Its 3D stacking approach directly challenges established 2D scaling roadmaps used in current enterprise processors.
This technology is in the early lab-prototype phase and is not yet available for commercial use or integration into consumer hardware. Industry partners and hardware engineers should monitor the 2030 sampling milestone for updates on manufacturing viability.
The takeaway
Nagare Labs is attempting to prove that oxide-based Z2RAM can scale density beyond current DRAM and SRAM limitations. Readers should monitor the startup's ability to stabilize its 3D hybrid bonding process as it moves toward the 2030 prototype sampling date.
Further reading
For more on the latest research and industry trends in chip architecture, see our Semiconductors section.
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