Agnisys and Axiomise Automate Network-on-Chip Verification
The partnership integrates design and verification tools to shorten development timelines for AI and GPU silicon architectures.
Updated on Oct. 26, 2026 in Semiconductors
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Agnisys and Axiomise have announced a partnership to integrate the IDS-NoC automated design tool with nocProve formal verification technology. This collaboration aims to streamline the creation and validation of network-on-chip architectures for high-performance silicon.
Why it matters
By combining automated chip generation with rigorous verification, this partnership seeks to accelerate time-to-market for complex AI processors and GPUs. The initiative addresses the increasing difficulty of ensuring quality and functional correctness in modern, large-scale chip designs.
The integration links IDS-NoC, an automated tool for generating network-on-chip structures, with nocProve, a formal verification technology used to prove design correctness. The platform replaces manual verification processes with automated specification-driven flows to reduce design errors.
The players
Agnisys
A developer of specification-driven chip automation software for semiconductor design workflows.
Axiomise
A provider of formal verification technology and consulting services for complex chip architectures.
The details
The integration connects specification-driven automation with formal verification—a mathematical process used to prove that a design satisfies certain properties without needing extensive simulation. IDS-NoC allows architects to specify network parameters, while nocProve applies formal analysis to identify functional bugs in the resulting NoC interconnect. This automated pipeline is intended to improve confidence in the reliability of silicon designs used in AI inference engines.
Timeline
October 26, 2026: Agnisys and Axiomise announced a partnership.
The Tech Race
Formal verification is increasingly critical as the complexity of AI-focused chip interconnects grows beyond what legacy simulation methods can handle. This partnership competes with internal design flows at major semiconductor firms that are racing to achieve higher functional reliability in shorter development cycles.
Engineers designing AI processors and GPU architectures can utilize this integrated platform to shorten their verification cycles. The capability is intended for design teams looking to improve design confidence for complex network-on-chip interconnects.
The takeaway
This partnership signifies a shift toward automating verification in the early stages of silicon design to avoid costly late-stage re-spins. Engineers should monitor for future performance benchmarks released by the companies to confirm if this integration reduces design verification time as expected.
Further reading
For more on the latest developments in chip design, visit our coverage of Semiconductors.
Source note: This article includes information reported by Design-reuse.
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