Advantest Showcased Semiconductor Test Tools in San Antonio
The Tokyo-based test equipment manufacturer presented its latest hardware and software ecosystems at the International Test Conference.
Updated on Oct. 13, 2026 in Semiconductors
Advantest Corporation is currently exhibiting its semiconductor test platforms at the 2026 International Test Conference in San Antonio, Texas. The company is demonstrating its SiConic ecosystem, System-Level Test platforms, and V93000 EXA Scale SoC Test System at booth 700.
Why it matters
The company’s participation reflects the ongoing industry effort to standardize testing protocols for complex 3D advanced packaging and system-level architectures. As chip complexity rises, automated test flow optimization has become critical for maintaining yield and performance standards.
Advantest is showcasing the V93000 EXA Scale SoC Test System and the Velocity automation solution, both of which are designed to support complex, multi-chip architectures that surpass the capabilities of traditional legacy test interfaces.
The players
Advantest Corporation
A Tokyo-headquartered manufacturer of automatic test equipment and software for the global semiconductor industry.
John Carulli
A technical professional moderating sessions on test flow optimization and industry analytics adoption.
Davette Berry
A presenter representing the technical program at the International Test Conference.
The details
Advantest utilizes the SmarTest 8 software suite to manage test flow optimization, allowing for the integration of SiConic, an ecosystem designed to unify disparate test hardware. The System-Level Test platforms are engineered to verify functionality by simulating real-world operating environments rather than relying solely on structural vector-based patterns. These systems enable engineers to perform end-to-end testing of 3D advanced packaging — a method of stacking integrated circuits vertically to increase density and performance.
Timeline
The 2026 International Test Conference runs from Oct. 11-16, 2026.
Davette Berry is scheduled to present on Oct. 14, 2026, at 10:30 a.m.
The Tech Race
Advantest’s presence at the event reflects its competitive effort to integrate software-driven analytics into the hardware-heavy semiconductor test market. The firm is positioning its SiConic ecosystem to gain a foothold against competing automated test platforms currently vying for dominance in 3D packaging verification.
Engineers and industry professionals attending the conference can interact directly with the hardware at booth 700 at the Grand Hyatt Regency Riverwalk. The technologies on display are intended for high-volume manufacturing environments rather than consumer-facing applications.
The takeaway
The event highlights the growing technical shift toward holistic, software-unified test ecosystems for modern silicon. Observers should track upcoming technical papers released by the International Test Conference to verify the real-world yields achieved by these new test methodologies.
Further reading
Learn more about the latest developments in testing and validation on our Semiconductors page.
More information
View complete technical specifications for the featured hardware on the Advantest corporate information and test solutions portal.
