Imec Explores 3D DRAM-on-GPU Integration
New research models a 3D memory architecture with integrated cooling cavities to overcome thermal limits in GPU design.
Updated on Oct. 26, 2026 in Semiconductors
In September 2026, researchers at Imec published a technical paper exploring a 3D DRAM-on-GPU architecture that stacks memory vertically above the processor. The design is currently in the research phase, utilizing simulations to evaluate thermal performance.
Why it matters
This research evaluates a potential alternative to 2.5D High Bandwidth Memory (HBM) and standard direct-stacked memory configurations. By shifting from lateral placement to vertical 3D volumetric integration, developers seek to overcome existing constraints in memory density and thermal management.
The study models a 3D memory architecture featuring cooling cavities integrated between vertically stacked DRAM dies. Simulations focused on optimizing stack height and cooling material properties to manage thermal load compared to standard 2.5D integration methods.
The players
Imec
A global research and development organization specializing in nanoelectronics, semiconductor scaling, and advanced packaging solutions.
The details
The design explores 3D volumetric integration where DRAM dies are rotated vertically above the GPU, rather than sitting alongside it as in 2.5D HBM (High Bandwidth Memory — a standard for high-performance memory chips). To mitigate heat, the researchers incorporated cooling cavities between the DRAM layers to facilitate dissipation. The team utilized package-level thermal simulations to evaluate how stack orientation and materials influence the thermal design envelope.
Timeline
September 2026: Imec published the technical paper Beyond HBM-on-GPU: Thermal Design Envelope for 3D Volumetric DRAM-on-GPU Integration.
The Tech Race
This architecture marks a departure from the industry-standard 2.5D HBM packaging currently used in top-tier AI accelerators. Imec’s work seeks to resolve the thermal bottleneck that has historically prevented the adoption of direct, vertically stacked memory on GPUs.
This research is currently in the simulation phase and does not have a commercial release timeline. If successful, the architecture could eventually inform future GPU design by enabling higher memory capacities in smaller device footprints.
The takeaway
Imec’s model suggests that vertical stacking could theoretically bypass the physical constraints of lateral memory placement. Future progress depends on the development of high-efficiency thermal interface materials that can support these dense 3D cooling cavities.
Further reading
For broader trends in memory density and packaging, see the latest developments in Semiconductors.
Source note: This article includes information reported by Semiconductor Engineering.
