Lam and imec Advance High-NA EUV Chip Patterning
The joint research effort targets manufacturing readiness for 20nm interconnects and next-generation chip architectures.
Updated on Oct. 28, 2026 in Semiconductors
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Lam Research and imec have announced a joint research collaboration focused on advancing 3D integration and high-NA EUV patterning technologies. This research-stage partnership aims to bridge the gap between laboratory-scale innovation and high-volume semiconductor manufacturing.
Why it matters
As AI workloads necessitate higher memory density and bandwidth, the industry requires new methods to scale advanced packaging and memory architectures. This collaboration targets the manufacturing readiness of next-generation gate-all-around and complementary FET designs.
The joint research achieved single-exposure high-NA EUV patterning for sub-20 nm ruthenium direct metal etch interconnects. The effort demonstrated 100% electrical yield for fork structures and over 90% yield for meander structures at a 20nm pitch.
The players
Lam Research
A global supplier of wafer fabrication equipment and services focused on deposition, etch, and clean processes for semiconductor manufacturers.
imec
A Belgium-based research and development organization specializing in nanoelectronics and digital technologies.
The details
The collaboration leverages Lam Research's specialized deposition and etch equipment alongside imec's integration infrastructure. Researchers are specifically testing the Aether dry resist platform within an imec high-NA EUV (Extreme Ultraviolet lithography, a technique using light with short wavelengths to print smaller features on chips) environment to evaluate resolution and defectivity. The work also covers thick dielectric deposition, asymmetric stress compensation, bevel deposition, and plasma dicing to validate advanced packaging techniques.
Timeline
October 28, 2026: Lam Research and imec announced their research collaboration.
The Tech Race
This partnership operates within the competitive race to operationalize high-NA EUV lithography for sub-20 nm feature sizes. By focusing on manufacturing readiness, the effort aims to outpace standard research cycles for gate-all-around and complementary FET architectures.
This research effort does not provide immediate hardware for current devices, as it remains in the laboratory validation phase. The outcomes will eventually inform the manufacturing processes used by foundries to produce the high-performance memory and logic chips required for future AI hardware.
The takeaway
The industry is accelerating the transition of high-NA EUV lithography from experimental patterning to reliable high-volume manufacturing. Readers should track upcoming research publications regarding the Aether platform's defectivity performance to gauge when these interconnect processes might reach commercial availability.
Further reading
For more on the industry's shift toward smaller feature sizes, visit our Semiconductors section.
Source note: This article includes information reported by Electronics Weekly.
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