New Memory Design Boosts AI Bandwidth 18x

Qualcomm's stacked LPDDR chip is research-stage, with Dragonfly AI250 sampling planned for the first half of 2027.

Updated on Nov. 2, 2026 in Semiconductors

Isometric editorial illustration of two stacked silicon wafers above an accelerator base, drawn in oxblood, teal, and mustard, depicting a memory-stacking chip design. — Qualcomm validated first-generation stacked-memory chip silicon in San Diego, targeting AI bandwidth limits, with Dragonfly AI250 sampling planned for the first half of 2027. AI Illustration. Upload story photo >

Qualcomm has validated first-generation High Bandwidth Compute (HBC) silicon in its San Diego labs, a research-stage result on a test sample rather than a shipped product. Qualcomm plans to sample its Dragonfly AI250 accelerator platform to enterprise customers and hyperscalers in the first half of 2027.

Why it matters

Large language models are shifting toward large-scale agentic inference, which is limited mainly by memory bandwidth rather than raw compute. HBC targets that bottleneck by stacking low-power LPDDR memory directly on an AI accelerator, a design aimed at avoiding the thermal and power costs of conventional HBM.

Qualcomm's validation test reported 18 times the memory bandwidth of DDR5 and over five times the bandwidth-per-watt of projected HBM4 specifications. The HBM4 efficiency figure came in slightly below the company's initial 6-fold projection, and the tested sample used only a two-layer DRAM stack.

The players

Qualcomm

A San Diego-based chipmaker known for mobile system-on-chip designs, now extending its Dragonfly AI accelerator line and custom Oryon-based server CPUs into data-center AI hardware.

The details

HBC stacks low-power LPDDR memory dies, a type of DRAM chip, directly on top of an active AI accelerator base die using direct wafer-to-wafer bonding, which fuses whole silicon wafers together rather than attaching individual chips. This vertical arrangement shortens the distance data must travel, since conventional HBM sends data across millimeter-scale distances off the chip package. Qualcomm integrated remapping and redundancy techniques into its manufacturing process so that defects in one stacked layer do not spread through the others.

First half of 2027: Dragonfly AI250 scheduled to sample to enterprise customers and hyperscalers
2027: Planned deployment of custom Oryon-based C1000 server CPU
2028: Planned next-gen HBC integration in the Dragonfly AI300 platform

The Tech Race

Qualcomm is positioning HBC as a lower-power alternative to HBM4, the stacked memory standard that current AI accelerators depend on. The comparison rests on Qualcomm's own projections for HBM4, which the company has not yet shown in shipping hardware.

HBC is not yet available to buyers; the earliest commercial sampling is planned for the first half of 2027. Companies running large AI inference workloads would be the first to evaluate it, if the four-layer commercial products match the validated results.

The takeaway

If HBC's bandwidth and efficiency figures hold in four-layer commercial products, memory design could shift toward stacking cheaper LPDDR for AI inference. Watch whether Qualcomm meets its first-half 2027 sampling target for the Dragonfly AI250.

What happens next

Qualcomm plans to sample the Dragonfly AI250 accelerator to enterprise customers and hyperscalers in the first half of 2027, which will show whether the validated bandwidth figures hold in commercial four-layer products.