SMTA Symposium Expands to Include 3D Integration Focus
The event rebranding signals a shift in semiconductor manufacturing toward advanced packaging and vertical stacking.
Updated on Oct. 21, 2026 in Semiconductors
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The Surface Mount Technology Association (SMTA) has renamed its Wafer-Level Packaging Symposium to the Microelectronics Packaging & Integration Symposium. The rebranding follows an expansion of the event scope to include advanced semiconductor packaging and 3D integration.
Why it matters
The change reflects the increasing complexity of electronic systems, where advanced integration is now a primary driver of performance. This shift signals a broader focus on the manufacturing processes required to stack and connect semiconductors more effectively.
The conference now centers on advanced semiconductor packaging and 3D integration processes, expanding beyond its traditional wafer-level focus. The event technical committee is currently curating research abstracts to define the updated performance benchmarks for these methods.
The players
Surface Mount Technology Association
An international organization that develops standards and holds technical symposia focused on electronic assembly and semiconductor manufacturing processes.
The details
The symposium covers the architecture and fabrication of complex microelectronics, specifically targeting the transition from traditional wafer-level packaging to heterogeneous 3D integration. In this context, 3D integration refers to vertical stacking and interconnecting of multiple dies—the bare silicon chips—within a single package to reduce latency and power consumption. The program now emphasizes the manufacturing hurdles associated with these dense, multi-layer assemblies.
Timeline
December 10, 2026: Deadline for submitting research abstracts.
February 9-11, 2027: Microelectronics Packaging & Integration Symposium.
The Tech Race
The symposium's rebranding aligns the event with the global industry shift toward heterogeneous chiplet integration. This follows the broader trend where advanced packaging has become a primary bottleneck and competitive differentiator for semiconductor performance scaling.
Researchers and process engineers should prepare to submit technical abstracts by December 10, 2026, for inclusion in the updated program. The conference will provide attendees in the San Francisco area with a venue to review the latest manufacturing benchmarks in 3D integration starting in February 2027.
The takeaway
The evolution of this symposium highlights how packaging has become central to chip performance as traditional scaling hits physical limits. Industry participants should monitor the finalized technical agenda in early 2027 to see which 3D integration processes are gaining the most traction in research.
Further reading
For broader trends in component manufacturing, visit Semiconductors.
More information
Submit your research or view the event details on the symposium website and abstract submission.
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